Explore projects

Coriolis VLSI CAD Tools

Alliance VLSI EDA. A complete set of GPL tools to design an ASIC.

kit of operating system for educational purpose

Coriolis VLSI CAD Tools

Static Timing Analyser

The bulk of the code developed during my PhD thesis « Efficient multiword matrix product algorithm using floating-point arithmetic over finite prime fields » (not yet defended/nor published).

Control of accuracy and debugging for CUDA applications

RankMerging version in C++ as coded by Dan Timsit in 2024.

Coriolis VLSI CAD Tools

Test de protocol de consensus c4m