Commit fd2c92f4 authored by Jean-Paul Chaput's avatar Jean-Paul Chaput
Browse files

* Change: In cumulus/plugins.chip.powerplane, when the vertical rail is

    large enough instead of creating one big via along the horizontal
    cell power lines, we create one big VIA at each end. To avoid to
    create too massive obstructions.
      But the thresold was too high for cmos45, leading to short with
    the clock tree trunk.
parent 5ba4c35d
......@@ -140,7 +140,7 @@ class HorizontalRail ( Rail ):
, self.axis + self.width//2 )
overlap = stripeBb.getIntersection( chunkBb )
if overlap.isEmpty(): continue
if overlap.getWidth() > 5*viaWidth:
if overlap.getWidth() > 2*viaWidth:
trace( 550, '\t| Large overlap={}\n'.format(overlap) )
via = BigVia( stripe.getNet()
, plane.getLayerDepth(stripe.getLayer())
......
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