Commit 927995e0 authored by Jean-Paul Chaput's avatar Jean-Paul Chaput
Browse files

Added support in "mk" for SkyWater130 + FlexLib.

* Added SkyWater130+Flexlib (sky130_c4m) to arlet6502 & ao68000.
parent 6d553efe
USE_DEBUG = No
USE_VALGRIND = No
export PDKMASTER_TOP = $(shell pwd)/../../../../C4M/open_pdk/C4M.Sky130
LOGICAL_SYNTHESIS = Yosys
PHYSICAL_SYNTHESIS = Coriolis
DESIGN_KIT = Sky130_C4M
YOSYS_FLATTEN = ao68000
YOSYS_SET_TOP = Yes
RM_CHIP = Yes
VST_FLAGS =
CHIP = chip
NETLISTS = ao68000
include ./mk/design-flow.mk
ao68000_cts_r.vst: ao68000.vst
$(call scl_cols,$(call c2env, $(VALGRIND_COMMAND) cgt -tV --script=doDesign))
ao68000_cts_r.gds: ao68000_cts_r.vst
-@echo "[INFO] Overriden default GDS rule (for use with FlexLib)."
blif: ao68000.blif
vst: ao68000.vst
gds: ao68000_cts_r.gds
`include "../rtl/alu_mult_generic.v"
`include "../rtl/memory_registers_generic.v"
`include "../rtl/ao68000.v"
../rtl/ao68000_microcode_b
\ No newline at end of file
from Hurricane import DebugSession
#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) )
#DebugSession.addToTrace( katana.getCell().getNet( 'cu_wr_rel_o(2)' ) )
#DebugSession.addToTrace( katana.getCell().getNet( 'xer_so_ok' ) )
# -*- Mode:Python -*-
import os
import socket
import helpers
NdaDirectory = None
if 'NDA_TOP' in os.environ:
NdaDirectory = os.environ['NDA_TOP']
if 'PDKMASTER_TOP' in os.environ:
PdkMasterTop = os.environ['PDKMASTER_TOP']
NdaDirectory = PdkMasterTop + '/libs.tech/coriolis/techno'
if not NdaDirectory:
hostname = socket.gethostname()
if hostname.startswith('lepka'):
NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno'
if not os.path.isdir(NdaDirectory):
print ('[ERROR] You forgot to mount the NDA '
'encrypted directory, stupid!')
else:
NdaDirectory = '/users/soft/techno/techno'
helpers.setNdaTopDir( NdaDirectory )
import Cfg
from CRL import AllianceFramework, RoutingLayerGauge
from helpers import overlay, l, u, n
from NDA.node130.sky130 import techno, FlexLib #, LibreSOCIO
techno.setup()
FlexLib.setup()
#LibreSOCIO.setup()
af = AllianceFramework.get()
with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
cfg.misc.catchCore = False
cfg.misc.minTraceLevel = 12300
cfg.misc.maxTraceLevel = 12400
cfg.misc.info = False
cfg.misc.paranoid = False
cfg.misc.bug = False
cfg.misc.logMode = True
cfg.misc.verboseLevel1 = True
cfg.misc.verboseLevel2 = True
cfg.etesian.graphics = 2
cfg.anabatic.topRoutingLayer = 'm4'
cfg.katana.eventsLimit = 4000000
af = AllianceFramework.get()
lg5 = af.getRoutingGauge('FlexLib').getLayerGauge( 5 )
lg5.setType( RoutingLayerGauge.PowerSupply )
env = af.getEnvironment()
env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
import sys
import traceback
import collections
import CRL
import helpers
helpers.loadUserSettings()
from helpers.io import ErrorMessage, WarningMessage
from helpers import trace, l, u, n
import plugins
from Hurricane import DbU, Breakpoint
from plugins.alpha.block.block import Block
from plugins.alpha.block.configuration import IoPin, GaugeConf
from plugins.alpha.block.spares import Spares
#from plugins.alpha.core2chip.libresocio import CoreToChip
from plugins.alpha.chip.configuration import ChipConf
from plugins.alpha.chip.chip import Chip
af = CRL.AllianceFramework.get()
powerCount = 0
def isiterable ( pyobj ):
if isinstance(pyobj,collections.Iterable): return True
return False
def doIoPowerCap ( flags ):
global powerCount
side = flags & IoPin.SIDE_MASK
if flags & IoPin.A_BEGIN:
ioPadPower = [ (side , None, 'power_{}'.format(powerCount), 'vdd' )
, (side , None, 'ground_{}'.format(powerCount), 'vss' )
, (side , None, 'ioground_{}'.format(powerCount), 'vss' )
, (side , None, 'iopower_{}'.format(powerCount), 'iovdd' )
]
else:
ioPadPower = [ (side , None, 'iopower_{}'.format(powerCount), 'iovdd' )
, (side , None, 'ioground_{}'.format(powerCount), 'vss' )
, (side , None, 'ground_{}'.format(powerCount), 'vss' )
, (side , None, 'power_{}'.format(powerCount), 'vdd' )
]
powerCount += 1
return ioPadPower
def doIoPinVector ( ioSpec, bits ):
v = []
if not isiterable(bits): bits = range(bits)
if not bits:
raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "bits" is neither a width nor an iterable.'
, '(bits={})'.format(bits)
] )
if len(ioSpec) == 5:
for bit in bits:
v.append(( ioSpec[0]
, ioSpec[1]
, ioSpec[2].format(bit)
, ioSpec[3].format(bit)
, ioSpec[4].format(bit) ))
elif len(ioSpec) == 6:
for bit in bits:
v.append(( ioSpec[0]
, ioSpec[1]
, ioSpec[2].format(bit)
, ioSpec[3].format(bit)
, ioSpec[4].format(bit)
, ioSpec[5].format(bit) ))
elif len(ioSpec) == 7:
for bit in bits:
v.append(( ioSpec[0]
, ioSpec[1]
, ioSpec[2].format(bit)
, ioSpec[3].format(bit)
, ioSpec[4].format(bit)
, ioSpec[5].format(bit)
, ioSpec[6].format(bit) ))
else:
raise ErrorMessage( 1, [ 'doIoPinVector(): Argument "ioSpec" must have between 5 and 7 fields ({})'.format(len(ioSpec))
, '(ioSpec={})'.format(ioSpec)
] )
return v
def scriptMain ( **kw ):
"""The mandatory function to be called by Coriolis CGT/Unicorn."""
global af
rvalue = True
try:
#helpers.setTraceLevel( 550 )
#Breakpoint.setStopLevel( 100 )
buildChip = False
cell, editor = plugins.kwParseMain( **kw )
cell = af.getCell( 'ao68000', CRL.Catalog.State.Logical )
if editor:
editor.setCell( cell )
editor.setDbuMode( DbU.StringModePhysical )
# ioPadsSpec, for I/O pad placement on a full chip.
ioPadsSpec = []
# West side (story).
ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_BEGIN )
ioPadsSpec += [ (IoPin.WEST , None, 'ack_i' , 'ack_i' , 'ack_i' )
, (IoPin.WEST , None, 'clk_i' , 'clk_i' , 'clk_i' )
, (IoPin.WEST , None, 'err_i' , 'err_i' , 'err_i' )
, (IoPin.WEST , None, 'reset_n' , 'reset_n' , 'reset_n' )
, (IoPin.WEST , None, 'rty_i' , 'rty_i' , 'rty_i' )
, (IoPin.WEST , None, 'blk_o' , 'blk_o' , 'blk_o' )
, (IoPin.WEST , None, 'blocked_o', 'blocked_o', 'blocked_o' )
, (IoPin.WEST , None, 'cyc_o' , 'cyc_o' , 'cyc_o' )
, (IoPin.WEST , None, 'reset_o' , 'reset_o' , 'reset_o' )
, (IoPin.WEST , None, 'rmw_o' , 'rmw_o' , 'rmw_o' )
, (IoPin.WEST , None, 'sgl_o' , 'sgl_o' , 'sgl_o' )
, (IoPin.WEST , None, 'stb_o' , 'stb_o' , 'stb_o' )
, (IoPin.WEST , None, 'we_o' , 'we_o' , 'we_o' )
]
ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'ipl_i_{}', 'ipl_i({})', 'ipl_i({})'), range(3) )
ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'bte_o_{}', 'bte_o({})', 'bte_o({})'), range(2) )
ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'cti_o_{}', 'cti_o({})', 'cti_o({})'), range(3) )
ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'fc_o_{}', 'fc_o({})', 'fc_o({})'), range(3) )
ioPadsSpec += doIoPinVector( (IoPin.WEST , None, 'sel_o_{}', 'sel_o({})', 'sel_o({})'), range(4) )
ioPadsSpec += doIoPowerCap( IoPin.WEST|IoPin.A_END )
# South side.
ioPadsSpec += doIoPowerCap( IoPin.SOUTH|IoPin.A_BEGIN )
ioPadsSpec += doIoPinVector( (IoPin.SOUTH, None, 'dat_i_{}', 'dat_i({})', 'dat_i({})'), range(32) )
ioPadsSpec += doIoPowerCap( IoPin.SOUTH|IoPin.A_END )
# East side.
ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_BEGIN )
ioPadsSpec += doIoPinVector( (IoPin.EAST, None, 'adr_o_{}', 'adr_o({})', 'adr_o({})'), range(2,32) )
ioPadsSpec += doIoPowerCap( IoPin.EAST|IoPin.A_END )
# North side.
ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_BEGIN )
ioPadsSpec += doIoPinVector( (IoPin.NORTH, None, 'dat_o_{}', 'dat_o({})', 'dat_o({})'), range(32) )
ioPadsSpec += doIoPowerCap( IoPin.NORTH|IoPin.A_END )
m1pitch = u(0.46)
m2pitch = u(0.51)
# ioPinsSpec, for peripheral pin placement as a standalone block.
ioPinsSpec = [ (IoPin.WEST |IoPin.A_BEGIN, 'ack_i' , 10*m1pitch, 0, 1)
#, (IoPin.WEST |IoPin.A_BEGIN, 'clk_i' , 20*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'err_i' , 30*m1pitch, 0, 1)
#, (IoPin.WEST |IoPin.A_BEGIN, 'reset_n' , 40*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'rty_i' , 50*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'blk_o' , 60*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'blocked_o', 70*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'cyc_o' , 80*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'reset_o' , 90*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'rmw_o' , 100*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'sgl_o' , 110*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'stb_o' , 120*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'we_o' , 130*m1pitch, 0, 1)
, (IoPin.WEST |IoPin.A_BEGIN, 'ipl_i({})', 140*m1pitch, 10*m1pitch, 3 )
, (IoPin.WEST |IoPin.A_BEGIN, 'bte_o({})', 170*m1pitch, 10*m1pitch, 2 )
, (IoPin.WEST |IoPin.A_BEGIN, 'cti_o({})', 190*m1pitch, 10*m1pitch, 3 )
, (IoPin.WEST |IoPin.A_BEGIN, 'fc_o({})', 220*m1pitch, 10*m1pitch, 3 )
, (IoPin.WEST |IoPin.A_BEGIN, 'sel_o({})', 260*m1pitch, 10*m1pitch, 4 )
, (IoPin.SOUTH|IoPin.A_BEGIN, 'dat_i({})', 10*m2pitch, 10*m2pitch, 32 )
, (IoPin.EAST |IoPin.A_BEGIN, 'adr_o({})', 10*m1pitch, 10*m1pitch, 32 )
, (IoPin.NORTH|IoPin.A_BEGIN, 'dat_o({})', 10*m2pitch, 10*m2pitch, 32 )
]
ao68000Conf = ChipConf( cell, ioPins=ioPinsSpec, ioPads=ioPadsSpec )
#ao68000Conf.cfg.etesian.bloat = 'Flexlib'
ao68000Conf.cfg.etesian.uniformDensity = True
ao68000Conf.cfg.etesian.aspectRatio = 1.0
# etesian.spaceMargin is ignored if the coreSize is directly set.
ao68000Conf.cfg.etesian.spaceMargin = 0.20
ao68000Conf.cfg.anabatic.searchHalo = 2
ao68000Conf.cfg.anabatic.globalIterations = 20
ao68000Conf.cfg.anabatic.topRoutingLayer = 'm4'
ao68000Conf.cfg.katana.hTracksReservedLocal = 6
ao68000Conf.cfg.katana.vTracksReservedLocal = 3
ao68000Conf.cfg.katana.hTracksReservedMin = 3
ao68000Conf.cfg.katana.vTracksReservedMin = 1
ao68000Conf.cfg.katana.trackFill = 0
ao68000Conf.cfg.katana.runRealignStage = True
ao68000Conf.cfg.block.spareSide = u(7*12)
#ao68000Conf.cfg.chip.padCoreSide = 'North'
#ao68000Conf.cfg.chip.use45corners = False
ao68000Conf.cfg.chip.useAbstractPads = True
ao68000Conf.cfg.chip.minPadSpacing = u(1.46)
ao68000Conf.cfg.chip.supplyRailWidth = u(35)
ao68000Conf.cfg.chip.supplyRailPitch = u(90)
ao68000Conf.editor = editor
ao68000Conf.useSpares = True
ao68000Conf.useClockTree = True
ao68000Conf.useHFNS = True
ao68000Conf.bColumns = 2
ao68000Conf.bRows = 2
ao68000Conf.chipName = 'chip'
ao68000Conf.chipConf.ioPadGauge = 'LibreSOCIO'
ao68000Conf.useHTree( 'clk_i', Spares.HEAVY_LEAF_LOAD )
ao68000Conf.useHTree( 'reset_n' )
if buildChip:
ao68000Conf.coreSize = ( u(130*12.0 ), u(120*12.0 ) )
ao68000Conf.chipSize = ( u( 40*90.0+5.0 + 2*214.0), u( 40*90.0+5.0 + 2*214.0) )
ao68000ToChip = CoreToChip( ao68000Conf )
ao68000ToChip.buildChip()
chipBuilder = Chip( ao68000Conf )
chipBuilder.doChipFloorplan()
rvalue = chipBuilder.doPnR()
chipBuilder.save()
else:
blockBuilder = Block( ao68000Conf )
rvalue = blockBuilder.doPnR()
blockBuilder.save()
except Exception as e:
helpers.io.catch( e )
rvalue = False
sys.stdout.flush()
sys.stderr.flush()
return rvalue
if __name__ == '__main__':
rvalue = scriptMain()
shellRValue = 0 if rvalue else 1
sys.exit( shellRValue )
../../../etc/mk
\ No newline at end of file
../rtl/ALU.v
\ No newline at end of file
../rtl/Arlet6502.v
\ No newline at end of file
export PDKMASTER_TOP = $(shell pwd)/../../../../C4M/open_pdk/C4M.Sky130
LOGICAL_SYNTHESIS = Yosys
PHYSICAL_SYNTHESIS = Coriolis
DESIGN_KIT = Sky130_C4M
YOSYS_FLATTEN =
YOSYS_SET_TOP = Yes
USE_DEBUG = No
RM_CHIP = Yes
VST_FLAGS =
CHIP = chip
NETLISTS = Arlet6502 \
cmpt_alu \
cmpt_cpu
include ./mk/design-flow.mk
chip_cts_r.vst: arlet6502.vst
$(call scl_cols,$(call c2env, $(VALGRIND_COMMAND) cgt -tV --script=doDesign))
chip_cts_r.gds: chip_cts_r.vst
-@echo "[INFO] Overriden default GDS rule (for use with FlexLib)."
blif: Arlet6502.blif
vst: arlet6502.vst
gds: chip_cts_r.gds
view: cgt-chip_r
view: cgt-arlet6502
from Hurricane import DebugSession
#DebugSession.addToTrace( katana.getCell().getNet( 'cu_issue_i' ) )
#DebugSession.addToTrace( katana.getCell().getNet( 'cu_wr_rel_o(2)' ) )
#DebugSession.addToTrace( katana.getCell().getNet( 'xer_so_ok' ) )
# -*- Mode:Python -*-
import os
import socket
import helpers
NdaDirectory = None
if 'NDA_TOP' in os.environ:
NdaDirectory = os.environ['NDA_TOP']
if 'PDKMASTER_TOP' in os.environ:
PdkMasterTop = os.environ['PDKMASTER_TOP']
NdaDirectory = PdkMasterTop + '/libs.tech/coriolis/techno'
if not NdaDirectory:
hostname = socket.gethostname()
if hostname.startswith('lepka'):
NdaDirectory = '/dsk/l1/jpc/crypted/soc/techno'
if not os.path.isdir(NdaDirectory):
print ('[ERROR] You forgot to mount the NDA '
'encrypted directory, stupid!')
else:
NdaDirectory = '/users/soft/techno/techno'
helpers.setNdaTopDir( NdaDirectory )
import Cfg
from CRL import AllianceFramework, RoutingLayerGauge
from helpers import overlay, l, u, n
from NDA.node130.sky130 import techno, FlexLib #, LibreSOCIO
techno.setup()
FlexLib.setup()
#LibreSOCIO.setup()
af = AllianceFramework.get()
with overlay.CfgCache(priority=Cfg.Parameter.Priority.UserFile) as cfg:
cfg.misc.catchCore = False
cfg.misc.minTraceLevel = 12300
cfg.misc.maxTraceLevel = 12400
cfg.misc.info = False
cfg.misc.paranoid = False
cfg.misc.bug = False
cfg.misc.logMode = True
cfg.misc.verboseLevel1 = True
cfg.misc.verboseLevel2 = True
cfg.etesian.graphics = 2
cfg.anabatic.topRoutingLayer = 'm4'
cfg.katana.eventsLimit = 4000000
af = AllianceFramework.get()
lg5 = af.getRoutingGauge('FlexLib').getLayerGauge( 5 )
lg5.setType( RoutingLayerGauge.PowerSupply )
env = af.getEnvironment()
env.setCLOCK( '^sys_clk$|^ck|^jtag_tck$' )
../rtl/cpu.v
\ No newline at end of file
../rtl/cpu_syncreset.v
\ No newline at end of file
import sys
import traceback
import CRL
import helpers
helpers.loadUserSettings()
from helpers.io import ErrorMessage, WarningMessage
from helpers import trace, l, u, n
import plugins
from Hurricane import DbU, Breakpoint
from plugins.alpha.block.block import Block
from plugins.alpha.block.configuration import IoPin, GaugeConf
from plugins.alpha.block.spares import Spares
#from plugins.alpha.core2chip.libresocio import CoreToChip
from plugins.alpha.chip.configuration import ChipConf
from plugins.alpha.chip.chip import Chip
af = CRL.AllianceFramework.get()
def scriptMain ( **kw ):
"""The mandatory function to be called by Coriolis CGT/Unicorn."""
global af
rvalue = True
try:
#helpers.setTraceLevel( 540 )
#Breakpoint.setStopLevel( 101 )
buildChip = False
cell, editor = plugins.kwParseMain( **kw )
cell = af.getCell( 'arlet6502', CRL.Catalog.State.Logical )
if editor:
editor.setCell( cell )
editor.setDbuMode( DbU.StringModePhysical )
ioPadsSpec = [ (IoPin.WEST , None, 'iopower_0' , 'iovdd' )
, (IoPin.WEST , None, 'ioground_0' , 'vss' )
, (IoPin.WEST , None, 'di_0' , 'di(0)' , 'di(0)' )
, (IoPin.WEST , None, 'di_1' , 'di(1)' , 'di(1)' )
, (IoPin.WEST , None, 'di_2' , 'di(2)' , 'di(2)' )
, (IoPin.WEST , None, 'di_3' , 'di(3)' , 'di(3)' )
, (IoPin.WEST , None, 'power_0' , 'vdd' )
, (IoPin.WEST , None, 'ground_0' , 'vss' )
, (IoPin.WEST , None, 'di_4' , 'di(4)' , 'di(4)' )
, (IoPin.WEST , None, 'di_5' , 'di(5)' , 'di(5)' )
, (IoPin.WEST , None, 'di_6' , 'di(6)' , 'di(6)' )
, (IoPin.WEST , None, 'di_7' , 'di(7)' , 'di(7)' )
, (IoPin.WEST , None, 'ioground_1' , 'vss' )
, (IoPin.WEST , None, 'iopower_1' , 'iovdd' )
, (IoPin.SOUTH, None, 'iopower_2' , 'iovdd' )
, (IoPin.SOUTH, None, 'ioground_2' , 'vss' )
, (IoPin.SOUTH, None, 'do_0' , 'do(0)' , 'do(0)' )
, (IoPin.SOUTH, None, 'do_1' , 'do(1)' , 'do(1)' )
, (IoPin.SOUTH, None, 'do_2' , 'do(2)' , 'do(2)' )
, (IoPin.SOUTH, None, 'do_3' , 'do(3)' , 'do(3)' )
, (IoPin.SOUTH, None, 'do_4' , 'do(4)' , 'do(4)' )
, (IoPin.SOUTH, None, 'do_5' , 'do(5)' , 'do(5)' )
, (IoPin.SOUTH, None, 'do_6' , 'do(6)' , 'do(6)' )
, (IoPin.SOUTH, None, 'do_7' , 'do(7)' , 'do(7)' )
, (IoPin.SOUTH, None, 'a_0' , 'a(0)' , 'a(0)' )
, (IoPin.SOUTH, None, 'a_1' , 'a(1)' , 'a(1)' )
, (IoPin.SOUTH, None, 'iopower_3' , 'iovdd' )
, (IoPin.SOUTH, None, 'ioground_3' , 'vss' )
, (IoPin.EAST , None, 'iopower_4' , 'iovdd' )
, (IoPin.EAST , None, 'ioground_4' , 'vss' )
, (IoPin.EAST , None, 'a_2' , 'a(2)' , 'a(2)' )
, (IoPin.EAST , None, 'a_3' , 'a(3)' , 'a(3)' )
, (IoPin.EAST , None, 'a_4' , 'a(4)' , 'a(4)' )
, (IoPin.EAST , None, 'a_5' , 'a(5)' , 'a(5)' )
, (IoPin.EAST , None, 'a_6' , 'a(6)' , 'a(6)' )
, (IoPin.EAST , None, 'a_7' , 'a(7)' , 'a(7)' )
, (IoPin.EAST , None, 'power_1' , 'vdd' )
, (IoPin.EAST , None, 'ground_1' , 'vss' )
, (IoPin.EAST , None, 'a_8' , 'a(8)' , 'a(8)' )
, (IoPin.EAST , None, 'a_9' , 'a(9)' , 'a(9)' )
, (IoPin.EAST , None, 'a_10' , 'a(10)' , 'a(10)' )
, (IoPin.EAST , None, 'a_11' , 'a(11)' , 'a(11)' )
, (IoPin.EAST , None, 'a_12' , 'a(12)' , 'a(12)' )
, (IoPin.EAST , None, 'a_13' , 'a(13)' , 'a(13)' )
, (IoPin.EAST , None, 'ioground_5' , 'vss' )
, (IoPin.EAST , None, 'iopower_5' , 'iovdd' )
, (IoPin.NORTH, None, 'iopower_6' , 'iovdd' )
, (IoPin.NORTH, None, 'ioground_6' , 'vss' )
, (IoPin.NORTH, None, 'irq' , 'irq' , 'irq' )
, (IoPin.NORTH, None, 'nmi' , 'nmi' , 'nmi' )
, (IoPin.NORTH, None, 'rdy' , 'rdy' , 'rdy' )
, (IoPin.NORTH, None, 'power_2' , 'vdd' )
, (IoPin.NORTH, None, 'ground_2' , 'vss' )
, (IoPin.NORTH, None, 'clk' , 'clk' , 'clk' )
, (IoPin.NORTH, None, 'reset' , 'reset' , 'reset' )
, (IoPin.NORTH, None, 'we' , 'we' , 'we' )
, (IoPin.NORTH, None, 'a_14' , 'a(14)' , 'a(14)' )
, (IoPin.NORTH, None, 'a_15' , 'a(15)' , 'a(15)' )
, (IoPin.NORTH, None, 'ioground_7' , 'vss' )
, (IoPin.NORTH, None, 'iopower_7' , 'iovdd' )
]
m1pitch = u(0.46)
m2pitch = u(0.51)
ioPinsSpec = [ (IoPin.WEST |IoPin.A_BEGIN, 'di({})' , 10*m1pitch, 10*m1pitch, 8)
, (IoPin.WEST |IoPin.A_BEGIN, 'do({})' , 15*m1pitch, 10*m1pitch, 8)
, (IoPin.EAST |IoPin.A_BEGIN, 'a({})' , 10*m1pitch, 10*m1pitch, 16)
#, (IoPin.NORTH|IoPin.A_BEGIN, 'clk' , 100*m2pitch, 0 , 1)
, (IoPin.NORTH|IoPin.A_BEGIN, 'irq' , 110*m2pitch, 0 , 1)
, (IoPin.NORTH|IoPin.A_BEGIN, 'nmi' , 120*m2pitch, 0 , 1)
, (IoPin.NORTH|IoPin.A_BEGIN, 'rdy' , 130*m2pitch, 0 , 1)
, (IoPin.NORTH|IoPin.A_BEGIN, 'we' , 140*m2pitch, 0 , 1)
#, (IoPin.NORTH|IoPin.A_BEGIN, 'reset' , 150*m2pitch, 0 , 1)
]
#ioPinsSpec = []
arlet6502Conf = ChipConf( cell, ioPins=ioPinsSpec, ioPads=ioPadsSpec )
arlet6502Conf.cfg.viewer.pixelThreshold = 5
#arlet6502Conf.cfg.etesian.bloat = 'Flexlib'
arlet6502Conf.cfg.etesian.uniformDensity = True
arlet6502Conf.cfg.etesian.aspectRatio = 1.0
# etesian.spaceMargin is ignored if the coreSize is directly set.
arlet6502Conf.cfg.etesian.spaceMargin = 0.10
arlet6502Conf.cfg.anabatic.searchHalo = 2
arlet6502Conf.cfg.anabatic.globalIterations = 20
arlet6502Conf.cfg.anabatic.topRoutingLayer = 'm4'
arlet6502Conf.cfg.katana.hTracksReservedLocal = 6
arlet6502Conf.cfg.katana.vTracksReservedLocal = 3
arlet6502Conf.cfg.katana.hTracksReservedMin = 3
arlet6502Conf.cfg.katana.vTracksReservedMin = 1
arlet6502Conf.cfg.katana.trackFill = 0
arlet6502Conf.cfg.katana.runRealignStage = True
arlet6502Conf.cfg.block.spareSide = u(7*12)
#arlet6502Conf.cfg.chip.padCoreSide = 'North'
#arlet6502Conf.cfg.chip.use45corners = False
arlet6502Conf.cfg.chip.useAbstractPads = True
arlet6502Conf.cfg.chip.minPadSpacing = u(1.46)
arlet6502Conf.cfg.chip.supplyRailWidth = u(8.0)
arlet6502Conf.cfg.chip.supplyRailPitch = u(8.0)
arlet6502Conf.editor = editor
arlet6502Conf.useSpares = True
arlet6502Conf.useClockTree = True
arlet6502Conf.useHFNS = True
arlet6502Conf.bColumns = 2