Alliance Coriolis Toolkit and Checker merge requestshttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests2020-02-19T11:49:35+01:00https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/2Nsxlib dimensions2020-02-19T11:49:35+01:00Staf VerhaegenNsxlib dimensionsThis pull request fixes some odd dimensions in some of the nsxlib cells.
Few METAL1 lines with width not multiple of lambda and NWELL with left and right extension different from the other cells.
This is a follow-up to !1 but now from m...This pull request fixes some odd dimensions in some of the nsxlib cells.
Few METAL1 lines with width not multiple of lambda and NWELL with left and right extension different from the other cells.
This is a follow-up to !1 but now from my fork from the main alliance-check-toolkit.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/3Provide dummy user config file.2020-03-05T10:31:47+01:00Staf VerhaegenProvide dummy user config file.I define the needed environment variables inside a conda environment so I don't need them in the user config file. The file is needed though as otherwise make will abort.I define the needed environment variables inside a conda environment so I don't need them in the user config file. The file is needed though as otherwise make will abort.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/5Gitignore2020-03-05T10:35:23+01:00Staf VerhaegenGitignoreIgnore more generated files.
I also included two commit for dev tools I am using/testing: Jupyter lab and Visual Studio Code.Ignore more generated files.
I also included two commit for dev tools I am using/testing: Jupyter lab and Visual Studio Code.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/8Update counter bench for sky1302022-07-25T13:32:19+02:00Staf VerhaegenUpdate counter bench for sky130When the Sky130 harness is used the top level pins have to match the harness pin names. Do this by added a top cell that maps the counter pins to the harness pins.
The bench is now locates in sky130_c4m/harness allowing for alternative s...When the Sky130 harness is used the top level pins have to match the harness pin names. Do this by added a top cell that maps the counter pins to the harness pins.
The bench is now locates in sky130_c4m/harness allowing for alternative sky130 implementation next to the harness version.Jean-Paul ChaputJean-Paul Chaputhttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9Update Sky130 PDK2022-08-03T17:47:22+02:00Staf VerhaegenUpdate Sky130 PDKThis is update to current version of c4m-pdk-sky130.
I first committed the PDK as generated by PDKMaster then updated to files. This allows to easily update to new versions in the future.This is update to current version of c4m-pdk-sky130.
I first committed the PDK as generated by PDKMaster then updated to files. This allows to easily update to new versions in the future.Jean-Paul ChaputJean-Paul Chaputhttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/10Draft: SRAM block for ethmac2022-08-03T18:22:37+02:00Staf VerhaegenDraft: SRAM block for ethmacThis is a merge request under development. It is built on top of https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 and untested with previous version of Sky130. So https://gitlab.lip6.fr/vlsi-eda/alliance-check-to...This is a merge request under development. It is built on top of https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 and untested with previous version of Sky130. So https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 should be merged first before this one.
This patch it's meant for testing and further discussion. The blif generation with the sram block should work and update blif file is included in the patch. Also the pin segments should properly use Horizontal/Vertical. Things still to look at (points may be added from discussion):
- [ ] pin names
- [ ] blockage layerJean-Paul ChaputJean-Paul Chaputhttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/7Fix vdd rail placement2022-07-15T13:22:35+02:00Staf VerhaegenFix vdd rail placementA non-conformant placement of the vdd rail was found in cell
oa3ao322_x4.A non-conformant placement of the vdd rail was found in cell
oa3ao322_x4.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/6Made nmigen python interpreter configurable2022-07-15T13:22:35+02:00Staf VerhaegenMade nmigen python interpreter configurablehttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/4[WIP]nsxlib: Added sr latches2022-07-15T13:22:35+02:00Staf Verhaegen[WIP]nsxlib: Added sr latches> Both a NOR based and NAND based latch is provided with a _x1 and _x4 drive strength version for each.
Currently the check does not pass proof. It complains on logical loop inside the _ext.vhd file.
I need help on getting this through ...> Both a NOR based and NAND based latch is provided with a _x1 and _x4 drive strength version for each.
Currently the check does not pass proof. It complains on logical loop inside the _ext.vhd file.
I need help on getting this through sign-off check.
I tried two styles for the .vbe file, one for the srlatch* cells and another nsnrlatch* cell but the problem seems to be with the extracted netlist.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/1Verhaegen nsxlib dimension fixes2020-02-18T18:36:53+01:00Staf VerhaegenVerhaegen nsxlib dimension fixesI found some component widths that seem to be off-grid. Rounded them to nearest lambda multiple.
Also found some NWELL components that seem to not follow the cell template.
I found some component widths that seem to be off-grid. Rounded them to nearest lambda multiple.
Also found some NWELL components that seem to not follow the cell template.