Alliance Coriolis Toolkit and Checker merge requestshttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests2022-07-15T13:22:35+02:00https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/6Made nmigen python interpreter configurable2022-07-15T13:22:35+02:00Staf VerhaegenMade nmigen python interpreter configurablehttps://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/7Fix vdd rail placement2022-07-15T13:22:35+02:00Staf VerhaegenFix vdd rail placementA non-conformant placement of the vdd rail was found in cell
oa3ao322_x4.A non-conformant placement of the vdd rail was found in cell
oa3ao322_x4.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/4[WIP]nsxlib: Added sr latches2022-07-15T13:22:35+02:00Staf Verhaegen[WIP]nsxlib: Added sr latches> Both a NOR based and NAND based latch is provided with a _x1 and _x4 drive strength version for each.
Currently the check does not pass proof. It complains on logical loop inside the _ext.vhd file.
I need help on getting this through ...> Both a NOR based and NAND based latch is provided with a _x1 and _x4 drive strength version for each.
Currently the check does not pass proof. It complains on logical loop inside the _ext.vhd file.
I need help on getting this through sign-off check.
I tried two styles for the .vbe file, one for the srlatch* cells and another nsnrlatch* cell but the problem seems to be with the extracted netlist.https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/10Draft: SRAM block for ethmac2022-08-03T18:22:37+02:00Staf VerhaegenDraft: SRAM block for ethmacThis is a merge request under development. It is built on top of https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 and untested with previous version of Sky130. So https://gitlab.lip6.fr/vlsi-eda/alliance-check-to...This is a merge request under development. It is built on top of https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 and untested with previous version of Sky130. So https://gitlab.lip6.fr/vlsi-eda/alliance-check-toolkit/-/merge_requests/9 should be merged first before this one.
This patch it's meant for testing and further discussion. The blif generation with the sram block should work and update blif file is included in the patch. Also the pin segments should properly use Horizontal/Vertical. Things still to look at (points may be added from discussion):
- [ ] pin names
- [ ] blockage layerJean-Paul ChaputJean-Paul Chaput