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  • Jean-Paul Chaput's avatar
    More generic H-Tree support to accomodate the LS180 PLL internal clock. · 205a6877
    Jean-Paul Chaput authored
    The H-Tree support is now allowed for any net, not only the clocks and
    not only top-level nets. This allow to better management of the LS180
    internal clock signal.
    
    * New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
        of the function to allow the user to select nets that will *not*
        be flattened. This makes the NoClockFlatten flag effectively obsolete,
        we keep it for backward compatibility.
          The net names can be of non top level ones. In that case, they must
        use the name an HyperNet will get (the Occurrence name). For example:
             "instance1.instance2.deep_net_name".
    * New: In PyCell, update the wrapper for the new parameter of flattenNets(),
        new utility function pyListToStringSet() to translate a Python list into
        a C++ set of names.
    * New: In EtesianEngine, add support for a list of nets to be excluded
        from the flattening procedure. Those excluded nets will also be
        excludeds from the Coloquinte nets *and* HFNS synthesis, as they
        are likely to be manageds by a H-Tree.
    * Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
        flagged as manually detailed route.
    * New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
        on nets that are already fixed or detaled route. This replace the
        clock exclusion.
    * New: In cumulus/plugins.{block,htree,chip}, replace the concept
        of clock-tree by the more generic H-Tree. That is, we can ask the P&R
        to create H-Tree on any net of the design, not only the ones matcheds
        as clock. The net does not even need to be top-level.
          This is to manage the PLL internal clock generated by the PLL in
        the LS180 chip.
          Start to change all reference to "clock" into "H-Tree".
    * Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
        there was an inversion of the H & V routing gauges to compute the
        track into which put the H-Tree center to corona edge wiring.
          This was causing tracks to be used twice, seen in the ao68000 test
        bench.
    205a6877