Add VHDL "ref" keyword to CRL::NamingScheme. Cleanup BlifParser debug.

crlcore/src/ccore/blif/BlifParser.cpp

@@ -741,8 +741,6 @@ namespace {
         //   cerr << "sm0 plug:" << plug->getMasterNet()->getName() << " => net:" << net->getName() << endl;
         // }
 
-        cerr << "plugNet=" << (void*)plugNet << endl;
-        cerr << "plug->getMasterNet()=" << (void*)(plug->getMasterNet()) << endl;
         if (plugNet->isSupply() and not plug->getMasterNet()->isSupply()) {
           ostringstream message;
           message << "In " << instance << "\n          "

crlcore/src/ccore/toolbox/NamingScheme.cpp

@@ -61,6 +61,7 @@ namespace CRL {
   // VHDL reserved keywords (scalar).
     if (loweredName == "in"   ) return "in_v";
     if (loweredName == "out"  ) return "out_v";
+    if (loweredName == "ref"  ) return "ref_v";
     if (loweredName == "inout") return "inout_v";
     if (loweredName == "true" ) return "bool_true";
     if (loweredName == "false") return "bool_false";