1. 04 Jun, 2021 1 commit
  2. 02 Jun, 2021 6 commits
  3. 30 May, 2021 2 commits
    • Jean-Paul Chaput's avatar
    • Jean-Paul Chaput's avatar
      More generic H-Tree support to accomodate the LS180 PLL internal clock. · 205a6877
      Jean-Paul Chaput authored
      The H-Tree support is now allowed for any net, not only the clocks and
      not only top-level nets. This allow to better management of the LS180
      internal clock signal.
      
      * New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
          of the function to allow the user to select nets that will *not*
          be flattened. This makes the NoClockFlatten flag effectively obsolete,
          we keep it for backward compatibility.
            The net names can be of non top level ones. In that case, they must
          use the name an HyperNet will get (the Occurrence name). For example:
               "instance1.instance2.deep_net_name".
      * New: In PyCell, update the wrapper for the new parameter of flattenNets(),
          new utility function pyListToStringSet() to translate a Python list into
          a C++ set of names.
      * New: In EtesianEngine, add support for a list of nets to be excluded
          from the flattening procedure. Those excluded nets will also be
          excludeds from the Coloquinte nets *and* HFNS synthesis, as they
          are likely to be manageds by a H-Tree.
      * Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
          flagged as manually detailed route.
      * New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
          on nets that are already fixed or detaled route. This replace the
          clock exclusion.
      * New: In cumulus/plugins.{block,htree,chip}, replace the concept
          of clock-tree by the more generic H-Tree. That is, we can ask the P&R
          to create H-Tree on any net of the design, not only the ones matcheds
          as clock. The net does not even need to be top-level.
            This is to manage the PLL internal clock generated by the PLL in
          the LS180 chip.
            Start to change all reference to "clock" into "H-Tree".
      * Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
          there was an inversion of the H & V routing gauges to compute the
          track into which put the H-Tree center to corona edge wiring.
            This was causing tracks to be used twice, seen in the ao68000 test
          bench.
      205a6877
  4. 27 May, 2021 1 commit
  5. 25 May, 2021 2 commits
  6. 22 May, 2021 7 commits
  7. 13 May, 2021 1 commit
    • Jean-Paul Chaput's avatar
      Add a "forced halo" to diode clusters. · 8ce16add
      Jean-Paul Chaput authored
      When a long *horizontal* wire connect to a cluster, an antenna effect
      may be created *before* the METAL3 is deposited, if the cluster's diode
      is not *directly* connected to the gate through *only* METAL2. So, we
      add a "forced halo" where the long horizontal connecting wires will be
      broken by a diode *near* the gate. This problem do not occur for long
      connecting METAL3, as the diode will be connected by then. Note that
      we are hard-coding the gauge routing direction in the algorithm.
        With that modification, only one antenna effect remains in LibreSOC
      LS180. May be corrected by post-treatement.
      
      * New: In Anabatic::DiodeCluster::mergeForcedhalo() add specific secondary
          areas where diode must be insterted in addition to the one of the
          RroutingPad cluster. To "isolate" the cluster from long horizontal
          wires.
      8ce16add
  8. 12 May, 2021 1 commit
    • Jean-Paul Chaput's avatar
      Fix, again, the save procedure in cumulus/plugins.chip & block. · 7ffe7511
      Jean-Paul Chaput authored
      * Bug: In cumulus/plugins.chip.Chip.save(), now completely delegate the
          saving procedure to the base class (i.e. Block.save() which is
          BlockConf.save()).
      * Bug/Change: In cumulus/plugins.block.configuration.BlockConf.save(),
          Now manage all the configutation, whether it is a simple block or
          a whole chip.
            In the case of a whole chip we must force the saving on both
          chip and corona as the later, being P&R will be seen as a terminal
          block and not recursively saved.
      7ffe7511
  9. 11 May, 2021 6 commits
    • Jean-Paul Chaput's avatar
      Create clusters for wire only chunks and add diodes if they are too long. · c80e99c0
      Jean-Paul Chaput authored
      Protecting clusters of sinks is not enough. There can be very long
      wires that far exceed the protection capacity of one diode. Instead
      of putting a bunch of diodes near the sinks, we choose to put them
      regularly along the interconncting wires.
        With this approach we are down to 7 antenna violations on LibreSOC
      LS180 test chip.
        This will get less good results on arlet6502 & ao6800 because of the
      core being a long way from the I/O pads. Should create jumpers on thoses,
      but it is for later.
      c80e99c0
    • Jean-Paul Chaput's avatar
      Ignore short overlaping same-net segments in realign stage. · 7ad26f1a
      Jean-Paul Chaput authored
      * Change: In Track::addOverlapCost(), in some configuration, we can
          have two overlapping short segments that can *both* be realigned.
          But they prevent that because we account their shared length on
          the track.
            So now, in realign mode only, do not account same-net shared
          length if the segment length is less than *two perpandicular pitches*.
            This helps the antenna protection by making the diode connected
          directly to METAL2 long stripes, and not keeping them isolated.
      7ad26f1a
    • Jean-Paul Chaput's avatar
    • Jean-Paul Chaput's avatar
      Fix memory corruption due to the deletion of unused spare buffers. · 28c8af27
      Jean-Paul Chaput authored
      * In cumulus/plugins.block.Block.{place,doPnr}(), reorder the
          feed insertion and spare buffer deletion call. Formerly, we
          were :
            1. Creating spare buffersa (Python).
            2. Placing (C++)
            3. Adding feeds (EtesianEngine::toHurricane() call) (C++).
            4. Removing unused spare buffers (Python).
         So, step 4 was *not* informing the C++ placement data-structure
         created at step 3 of the change. Resulting in occurrences using
         deleted Entities (Instance).
           Now we swap step 3. and 4. so toHurricane() is called *after*
         any Python managed change is done.
           Ideally, what we should implement is a way for Python to inform
         the C++ data-structure. No real problem here, but time...
      28c8af27
    • Jean-Paul Chaput's avatar
      Fix memory corruption in Etesian::Area, separate it's creation. · 972787c8
      Jean-Paul Chaput authored
      * In Etesian::Slice::createDiodeUnder(), delete the Instance *after*
          removing the tile referring it. This was working, unless we
          active the debug mode which tries to print the Tile's instance.
      * In EtesianEngine::place(), no longer call toHurricane() at the
          end of the placement. Must now be done as a separate step.
          Exported to Python interface.
            This fix is related to the spare buffer removal memory
          corruption
      972787c8
    • Jean-Paul Chaput's avatar
  10. 09 May, 2021 2 commits
    • Jean-Paul Chaput's avatar
      Do not account self-segment in track cost calculation. · c137c1ac
      Jean-Paul Chaput authored
      * Change: In Katana::Track::addOverlapCost(), if an overlaping segment
          is owned by the net *and* is the one we want to insert, do not take
          it into account in the shared length.
            This case never occured before we introduced the "realign" stage,
          as a to be inserted segment, was, by definition, not already
          inserted in a track. But in the realign stage, it is. So we should
          not account it when computing the insertion cost in the track it
          is already in. This was preventing short segments (less than a
          pitch) to be correctly re-aligned.
            And, as a side effect, preventing the antenna/diodes to work as
          intended (diode connected at METAL3 layer while the antenna occur
          at METAL2 layer).
      c137c1ac
    • Jean-Paul Chaput's avatar
  11. 04 May, 2021 2 commits
    • Jean-Paul Chaput's avatar
      Stop saving AP files when working in real mode. · 1fb433d9
      Jean-Paul Chaput authored
      * Change: In cumulus/plugins.block.configuration.Configuration.save()
          and cumulus/plugins.chip.Chip.save(), according to the kind of
          routing gauge we are using (symbolic or real), either recursively
          save all the layouts (AP symbolic files) or only the top-level
          GDSII (which embed all the hierarchy) one.
      1fb433d9
    • Jean-Paul Chaput's avatar
      Complete rewrite of the diode insertion algorithm. · bb5c9924
      Jean-Paul Chaput authored
      First part of the antenna effect protection : diode insertions.
      Anabatic::antennaProtect(Net*) and it's supporting infrastructure
      has been rewritten & simplificated. Must be used in conjuction
      with the "Flexlib" bloat model of Etesian. A cursory description
      of the algorithm has been added in the source file.
      
      * New: GCell::hasNet() to tell if net is going through a GCell,
          either as a straigth wire or has a local GContact (turn,
          branch, terminal).
      * New: Etesian::BloatFlexib class (tagged "Flexlib") suited for
          flexlib uses. It is derived from "nsxlib".
            To have enough space to insert all the wanted diodes, we
          enlarge "mx2_x2" & "mx3_x2" of resp. 1 and 2 pitches.
            This is an empiric finding, Yosys seems very fond of thoses
          gates and we often see them underneath area where no space
          was available to put a diode... May need some more fine grained
          analysis.
      bb5c9924
  12. 28 Apr, 2021 4 commits
  13. 24 Apr, 2021 5 commits