1. 12 Jun, 2021 3 commits
  2. 11 Jun, 2021 4 commits
  3. 10 Jun, 2021 5 commits
  4. 09 Jun, 2021 1 commit
    • Jean-Paul Chaput's avatar
      Adjust blockage area over SRAM. · 7961aab0
      Jean-Paul Chaput authored
      * Change: In cumulus/plugins.block.macro, the METAL2 blockage was
          allowing horizontal tracks to be used but the METAL3 blockage
          was conflicting with the end of the perpandiculars.
            The router was not able to manage that, so we slightly expand
          the METAL2 blockage to encompass the unreachable track.
            For the same reason, add a METAL4 blockage over METAL2.
  5. 08 Jun, 2021 3 commits
    • Jean-Paul Chaput's avatar
      Add jumpers (antenna protection) on I/O pads and SRAM macro-block. · 92a3e32a
      Jean-Paul Chaput authored
      * New: In cumulus/plugins.chip.pads, add METAL5 jumpers on all wires
          going to/from the I/O pads on the East & West side. This is a
          quick hack as:
            1. We should put it also on North/South, but no violation
               happens here.
            2. We should put it on *ouput* wire only (for only those are
               connected to transistors gates).
      * New: In cumulus/plugins.chip.macro, put jumpers on the East side
          connectors for the SRAM block. Also a quick hack, not robust for
          anything else than the SRAM.
    • Jean-Paul Chaput's avatar
      Compensate diodes between RP clusters & wire clusters. · dd49a185
      Jean-Paul Chaput authored
      In Anabatic::AntennaProtect, when we cannot insert enough diodes
      under a wire cluster. Which makes it likely very long and over an
      area where diodes cannot be inserted (chip border close to I/O pads
      or over a macro-block). Request extra diode insertion on it's
      connecting RoutingPad clusters.
      * New: In Anabatic::DiodeCluster, add a "forced diode" counter for
          extra diodes inertions. Only used in the DiodeRps derived class.
      * New: In Anabatic::DiodeCluster, add support for a cluster to know
          it's neighbors. Stored as indexes of the table being built in
      * New: In Anabatic::antennaProtect(Net*), when builing the WireCluster,
          also find it's neigbors. Store the index of the cluster a segment
          belongs to in clusterSegments.
    • Jean-Paul Chaput's avatar
  6. 06 Jun, 2021 3 commits
  7. 04 Jun, 2021 1 commit
  8. 02 Jun, 2021 6 commits
  9. 30 May, 2021 2 commits
    • Jean-Paul Chaput's avatar
    • Jean-Paul Chaput's avatar
      More generic H-Tree support to accomodate the LS180 PLL internal clock. · 205a6877
      Jean-Paul Chaput authored
      The H-Tree support is now allowed for any net, not only the clocks and
      not only top-level nets. This allow to better management of the LS180
      internal clock signal.
      * New: In Cell::flattenNets(Instance*,set<string>,uint64_t) new overload
          of the function to allow the user to select nets that will *not*
          be flattened. This makes the NoClockFlatten flag effectively obsolete,
          we keep it for backward compatibility.
            The net names can be of non top level ones. In that case, they must
          use the name an HyperNet will get (the Occurrence name). For example:
      * New: In PyCell, update the wrapper for the new parameter of flattenNets(),
          new utility function pyListToStringSet() to translate a Python list into
          a C++ set of names.
      * New: In EtesianEngine, add support for a list of nets to be excluded
          from the flattening procedure. Those excluded nets will also be
          excludeds from the Coloquinte nets *and* HFNS synthesis, as they
          are likely to be manageds by a H-Tree.
      * Change: In AnabaticEngine::_loadGrByNet(), now also skip nets that are
          flagged as manually detailed route.
      * New: In AnabaticEngine::antennaProtect(), do not try to insert diodes
          on nets that are already fixed or detaled route. This replace the
          clock exclusion.
      * New: In cumulus/plugins.{block,htree,chip}, replace the concept
          of clock-tree by the more generic H-Tree. That is, we can ask the P&R
          to create H-Tree on any net of the design, not only the ones matcheds
          as clock. The net does not even need to be top-level.
            This is to manage the PLL internal clock generated by the PLL in
          the LS180 chip.
            Start to change all reference to "clock" into "H-Tree".
      * Bug: In cumulus/plugins.chip.powerplanes.Builder._connectHTree(),
          there was an inversion of the H & V routing gauges to compute the
          track into which put the H-Tree center to corona edge wiring.
            This was causing tracks to be used twice, seen in the ao68000 test
  10. 27 May, 2021 1 commit
  11. 25 May, 2021 2 commits
  12. 22 May, 2021 7 commits
  13. 13 May, 2021 1 commit
    • Jean-Paul Chaput's avatar
      Add a "forced halo" to diode clusters. · 8ce16add
      Jean-Paul Chaput authored
      When a long *horizontal* wire connect to a cluster, an antenna effect
      may be created *before* the METAL3 is deposited, if the cluster's diode
      is not *directly* connected to the gate through *only* METAL2. So, we
      add a "forced halo" where the long horizontal connecting wires will be
      broken by a diode *near* the gate. This problem do not occur for long
      connecting METAL3, as the diode will be connected by then. Note that
      we are hard-coding the gauge routing direction in the algorithm.
        With that modification, only one antenna effect remains in LibreSOC
      LS180. May be corrected by post-treatement.
      * New: In Anabatic::DiodeCluster::mergeForcedhalo() add specific secondary
          areas where diode must be insterted in addition to the one of the
          RroutingPad cluster. To "isolate" the cluster from long horizontal
  14. 12 May, 2021 1 commit
    • Jean-Paul Chaput's avatar
      Fix, again, the save procedure in cumulus/plugins.chip & block. · 7ffe7511
      Jean-Paul Chaput authored
      * Bug: In cumulus/plugins.chip.Chip.save(), now completely delegate the
          saving procedure to the base class (i.e. Block.save() which is
      * Bug/Change: In cumulus/plugins.block.configuration.BlockConf.save(),
          Now manage all the configutation, whether it is a simple block or
          a whole chip.
            In the case of a whole chip we must force the saving on both
          chip and corona as the later, being P&R will be seen as a terminal
          block and not recursively saved.