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Coriolis VLSI EDA
Coriolis
Issues
Open
22
Closed
28
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50
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Title
enhancement of clock tree: ad-hoc, for dealing with external peripheral PHYs
#50
· created
Nov 17, 2021
by
Luke Leighton
0
updated
Nov 17, 2021
coriolisenv.py fails to identify shell if run from a script
#48
· created
Oct 01, 2021
by
Luke Leighton
1
updated
Oct 01, 2021
investigating PLL signal inversion in ls180
#47
· created
May 27, 2021
by
Luke Leighton
2
updated
May 27, 2021
soclayout9
#46
· created
Apr 21, 2021
by
Luke Leighton
0
updated
Apr 21, 2021
FreePDK45 first attempt to get LibreSOCIO vbe and ap files to complete FreePDK45-c4m PnR
#45
· created
Apr 21, 2021
by
Luke Leighton
0
updated
Apr 21, 2021
pllplaceholder in vst causes syntax error
#44
· created
Apr 20, 2021
by
Luke Leighton
0
updated
Apr 20, 2021
ghdl compilation of VST files: HFNS net names the same as instance names
#42
· created
Apr 14, 2021
by
Luke Leighton
4
updated
Apr 16, 2021
BigVia cannot create cut of via2 error using FreePDK45
#41
· created
Apr 12, 2021
by
Luke Leighton
16
updated
Apr 21, 2021
katana segfault
#39
· created
Apr 11, 2021
by
Luke Leighton
1
updated
Apr 18, 2021
ghdl compilation of VST files, port is marked incorrect as an input
#36
· created
Apr 02, 2021
by
Luke Leighton
8
updated
Apr 17, 2021
enhance new niolib plugin to accept True/False for pad direction (rather than a signal)
#32
· created
Nov 04, 2020
by
Luke Leighton
5
updated
Nov 04, 2020
syntax error in lvx
#31
· created
Oct 23, 2020
by
Luke Leighton
6
updated
Oct 25, 2020
add feature to core2chip to allow more external/internal power/ground pins p_(vss/vdd)(i/e)ck_(0/1/2....)
#29
· created
Oct 04, 2020
by
Luke Leighton
12
updated
Nov 30, 2020
Katana BUG (loops) in experiments9 soclayout
#25
· created
Aug 11, 2020
by
Luke Leighton
7
updated
Sep 14, 2020
segfault in running libresoc doDesign
#23
· created
Aug 05, 2020
by
Luke Leighton
4
updated
Aug 07, 2020
Signal Integrity (crosstalk)
#19
· created
Jun 17, 2020
by
Jean-Paul Chaput
Coriolis Features for Libre-SOC Test Chip
Aug 21, 2020
0
updated
Jul 06, 2020
Antenna Rule Compliance
#18
· created
Jun 17, 2020
by
Jean-Paul Chaput
Coriolis Features for Libre-SOC Test Chip
Aug 7, 2020
0
updated
Jul 06, 2020
Power Distribution Network
#17
· created
Jun 17, 2020
by
Jean-Paul Chaput
Coriolis Features for Libre-SOC Test Chip
Jul 24, 2020
0
updated
Jul 06, 2020
High Fan-Out Net Synthesis
#16
· created
Jun 17, 2020
by
Jean-Paul Chaput
Coriolis Features for Libre-SOC Test Chip
Jun 26, 2020
0
updated
Jul 06, 2020
feature-request: Etesian.create() and EtesianEngine.place() to accept a list of instances for placement
#12
· created
Apr 21, 2020
by
Luke Leighton
0
updated
Apr 21, 2020
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