ghdl compilation of VST files, nested names (signal zero_0, component zero_0) not allowed in VHDL2008

this one is documented here: https://github.com/ghdl/ghdl/issues/542

apparently only VHDL 2002 allowed nested names.

../vst_src/alu_alu0.vst:225:10: identifier "zero_0" already used for a declaration
../vst_src/alu_alu0.vst:311:3: previous declaration: component instance "zero_0"
../vst_src/alu_alu0.vst:267:42: component instance "zero_0" not allowed in an expression
../vst_src/alu_alu0.vst:268:42: component instance "zero_0" not allowed in an expression
../vst_src/alu_alu0.vst:312:21: component instance "zero_0" not allowed in an expression
ghdl: compilation error
```[alu_alu0.vst](/uploads/f2056a976b5b2302e455104bd35d9fe7/alu_alu0.vst)