enhancement of clock tree: ad-hoc, for dealing with external peripheral PHYs

https://bugs.libre-soc.org/show_bug.cgi?id=739#c15 https://bugs.libre-soc.org/show_bug.cgi?id=739#c16

a localised occurrence of externally-synchronised signals, from a PHY that generates its own digital clock, need to cross to the main clock domain for both input and output data.

however there are so many of them, and the clock so localised (right next to the IO pads) that creating a global H-Tree is unnecessary and inadviseable: for the Gigabit Router ASIC there would be 11 such clocks!

speeds of the external clocks are between 5 khz (JTAG at lowest setting), 400 khz (I2C slave), 2.5 / 25 / 125 mhz for 10/100/1000 Ethernet, 60 mhz for USB2 ULPI.

the speeds are not super-fast: the only questionable one is RGMII in Gigabit mode (125 mhz), however, fascinatingly, the situation where there is clock skew on both the TX and RX clock has been catered for in the design of the RGMII interface by adding two extra lines: TXDELAY and RXDELAY which introduce 2ns of clock delay in the PHY, and may be set if needed by the SoC.