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Expired
Milestone expired on Nov 28, 2020

Coriolis Features for Libre-SOC Test Chip
Milestone ID: 12

Timetable/schedule to implement the missing features in Coriolis to be able to build the Libre-SOC first test chip. The target technology is TSMC 180nm and the circuit is due for the end of november 2020.

  • Issues 4
  • Merge requests 0
  • Participants 1
  • Labels 0
0% complete
0%
Start date
No start date
Until
Nov 28 2020
Due date
Nov 28, 2020 (Past due)
4
Issues 4 New issue
Open: 4 Closed: 0
0
Merge requests 0
Open: 0 Closed: 0 Merged: 0
0
Releases
None
Reference: vlsi-eda/coriolis%"Coriolis Features for Libre-SOC Test Chip"