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Coriolis VLSI CAD Tools

Alliance VLSI EDA. A complete set of GPL tools to design an ASIC.

Test de protocol de consensus c4m

Static Timing Analyser

Control of accuracy and debugging for C/C++ and Fortran applications

This is the source code of the 2021 replication for ReScience of the paper "Speedup Graph Processing by Graph Ordering" by Hao Wei, Jeffrey Xu Yu, Can Lu, and Xuemin Lin, published in Proceedings of SIGMOD 2016.

RankMerging version in C++ as coded by Dan Timsit in 2024.

Mixed precision variant

Control of accuracy and debugging for CUDA applications

Uniform precision variant

Control of accuracy and debugging for Python applications

Coriolis VLSI CAD Tools

Control of accuracy and debugging for C/C++ applications relying on fixed-point arithmetic

kit of operating system for educational purpose