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A blockgraph for mesh networks

Coriolis VLSI CAD Tools

Alliance VLSI EDA. A complete set of GPL tools to design an ASIC.

Coriolis VLSI CAD Tools

Test de protocol de consensus c4m

Static Timing Analyser

Coriolis VLSI CAD Tools

Coriolis VLSI CAD Tools

This is the source code of the 2021 replication for ReScience of the paper "Speedup Graph Processing by Graph Ordering" by Hao Wei, Jeffrey Xu Yu, Can Lu, and Xuemin Lin, published in Proceedings of SIGMOD 2016.

Static Timing Analyser

kit of operating system for educational purpose