Coriolis VLSI CAD Tools
This is the source code of the 2021 replication for ReScience of the paper "Speedup Graph Processing by Graph Ordering" by Hao Wei, Jeffrey Xu Yu, Can Lu, and Xuemin Lin, published in Proceedings of SIGMOD 2016.
Static Timing Analyser
kit of operating system for educational purpose
A blockgraph for mesh networks
Test de protocol de consensus c4m
Alliance VLSI EDA. A complete set of GPL tools to design an ASIC.