core2chip.py generating chip.vst and chip_r.vst with conflicting signal names
very simple fix to try out, create a different (internal) net name for the intermediary signal. otherwise confusion results in GHDL --std=08
chip_r.vhd:430:10:error: multiple assignments for "sdram_dm_to_pad" offsets 0:0
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^
chip_r.vhd:430:10:note: this concerns these parts of the signal:
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^
chip_r.vhd:430:10:note: sdram_dm_to_pad(0)
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^
chip_r.vhd:430:10:error: multiple assignments for "sdram_dm_to_pad" offsets 1:1
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^
chip_r.vhd:430:10:note: this concerns these parts of the signal:
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^
chip_r.vhd:430:10:note: sdram_dm_to_pad(1)
signal sdram_dm_to_pad : bit_vector(1 downto 0);
^